Am 25.02.2011 11:00, schrieb Uwe Bonnes:
"Thomas" == Thomas Heller<theller@xxxxxxxxxx> writes:
...
Thomas> Is it known that the FT2232H sync fifo mode still has this
Thomas> problem? Could it be a driver (ftd2xx.dll) problem? Can it be
Thomas> that libftdi works better?
We are running at about 15 MByte/sec with libftdi. From the users of the
board I don't have reports about (repeated) single byte missed. In our case
this would mean that data packages no longer align.
I would have the same problem since I need to transfer
32-bit data packages.
What FPGA do you use. How do you achieve the harsh timing requirements of
the FT2232H? I wasn't able to achieve the required 5.5 ns OFFSET with
XC6SLX45-2 and had to relax 0.4 ns :
NET "usb_adbus<*>" OFFSET = OUT 5.94 ns AFTER "usb_clk_in";
NET "usb_wr_n" OFFSET = OUT 5.94 ns AFTER "usb_clk_in";
NET "usb_txe_n" OFFSET = IN 9.5 ns VALID 10.5 ns BEFORE "usb_clk_in";
I use a xc3s200a-4 and I can meet the timing requirements.
A DCM is used to mirror the 60 MHz clock with zero delay; also
I had to make sure that the data-input, data-output, and control
signals registers (WRn, RDn) are put into IOBs.
I have written the constraints in a different way:
NET "RDn" OFFSET = OUT 11 ns BEFORE "clk60" ;
NET "RXFn" OFFSET = IN 9.52 ns BEFORE "clk60" HIGH;
NET "WRn" OFFSET = OUT 11 ns BEFORE "clk60" ;
NET "AD<*>" OFFSET = OUT 11 ns BEFORE "clk60" ;
NET "TXEn" OFFSET = IN 9.52 ns BEFORE "clk60" HIGH;
but they are all met:
RDn 11.058 ns
TXEn 9.119 ns
AD<*> 12.700 ns ... 12.758 ns
RXFn 7.275 ns
WRn 12.732 ns
It also took me some time to get teh state machine right for the case when
the FT signals FIFIO full...
I'll look into this.
Thanks,
Thomas
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