Thanks for your answer Berni,
I think this problem seems to originate form some sort of miss understanding.
SPI defines four modes, each with its own data in and data out. So your listing
mentions
only two SPI modes.
All four are described for example in AN_114 page 3:
<quote>
For CPOL = 0, the base (inactive) level of SCLK is 0.
In this mode:
- When CPHA = 0, data will be read in on the rising edge of SCLK,
and data will be clocked out on the falling edge
of SCLK.
- When CPHA = 1, data will be read in on the falling edge of SCLK,
and data will be clocked out on the rising edge
of
SCLK.
For CPOL = 1, the base (inactive) level of SCLK is 1.
In this mode:
- When CPHA = 0, data will be read in on the falling edge of SCLK,
and data will be clocked out on the rising edge
of
SCLK.
- When CPHA = 1, data will be read in on the rising edge of SCLK,
and data will be clocked out on the falling edge
of SCLK.
Mode CPOL CPHA
0 0 0
1 0 1
2 1 0
3 1 1
</quote>
This definition matches the standard definition of several other documents (in
wikipedia is for example a nice picture with scope traces).
For example my ads1255, which I would like to connect seems to need SPI mode 1
(CPOL=0, CPHA=1) which is missing from your
definition.
=> This leads me back to the initial question. Does the FT4232H only support
the
two modes you mentioned below,
or does it support all four as defined above???
As for your idea regarding the 'Set Data' command, the whole test command I
issue is:
80 0 db 11 2 0 53 0 82 80 8 db
ffffffffff fffffffffff
the flanking 'Set Data' commands ensure that the chip select (!CS) is actually
low for the command, the spi write is just a test to see if the ADC takes a new
sample rate, but it 0x11 seems to be mode 0, which my adc does not understand.
Just to make sure, I will try to add the 0x82 command...
Best
Stefan
----- Ursprüngliche Mail ----
Von: Berni Joss <berni.joss@xxxxxxxxxx>
An: libftdi@xxxxxxxxxxxxxxxxxxxxxxx
CC: stefan harjes <stefanharjes@xxxxxxxx>
Gesendet: Freitag, den 18. Februar 2011, 14:44:42 Uhr
Betreff: Re: only two of four SPI modes supported by FT4232H??
On Fri, Feb 18, 2011 at 02:49:32PM +0000, stefan harjes wrote:
> When I use a scope, no matter which write/read command I issue to the MPSSE
> engine, I have not been able to get the SPI mode 1 (initial clock polarity 0,
> data out on rising edge).
Did you try setting the state of the clock pin to the idle state, e.g. with the
"Set Data" commands 0x80/0x82, before clocking the data?
I have not used MPSSE for SPI ... but it seems all 4 modes should be supported.
On page 7 of AN_108 version 1.21 I read:
<quote>
The TCK/CK output pin will do an XOR of the current state of the CLK pin twice.
This means that if the clock pin is set low, then the clock will go high then
low to be 1 clock cycle. If the clock pin were set high, then the clock will go
low then high to be 1 clock cycle.
The implications of this are:
If the clock starts at an idle state of logic 0:
Data can be clocked out on a –ve clock edge.
Data can be clocked in on a +ve clock edge.
If the clock starts at an idle state of logic 1:
Data can be clocked out on a +ve clock edge.
Data can be clocked in on a -ve clock edge.
</quote>
Kind regards,
Berni
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