Andrey,
60 MHz is the clock rate. At 8 bits per clock, this would appear to be
the 480 Mb/sec USB 2.0 data rate, but, because of the bit packing, the
maximum realizable data rate is really about 53 MB/sec (personal
experience and other reports). The chips include a "data enable" or
similar to gate the incoming data based on the bus availability,
serialized data rate, etc.
Rodney
On 04/29/2015 09:41 AM, Uwe Bonnes wrote:
Andrey> Dear libftdi developers and users, I believe one can use
Andrey> examples/stream_test.c [1] as an example how to exploit the
Andrey> ft2232h as an up to 60 MHz logic analyzer. Could you clarify,
Andrey> what pins exactly are sampled, e.g. only AD0..AD7? It would be
Andrey> nice, if you could also add this info into the source code.
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