>>>>> "Andrey" == Andrey Gursky <andrey.gursky@xxxxxxxxx> writes:
Andrey> Dear libftdi developers and users, I believe one can use
Andrey> examples/stream_test.c [1] as an example how to exploit the
Andrey> ft2232h as an up to 60 MHz logic analyzer. Could you clarify,
Andrey> what pins exactly are sampled, e.g. only AD0..AD7? It would be
Andrey> nice, if you could also add this info into the source code.
The final clarification is the datasheet. Have a look at it.
FT2232H synchronous FIFO mode will always sample a 60 MHz (CLKOUT
frequency). Probably the RX buffer will soon be full, RXF will assert and
sampling will stop until the RX buffer has been transfered to the host. Than
sampling will restart, signaled by RXF. This will give no sensible sampling
for a logic analyser. Toggling RD_N in a 1:2 or 1:3 or higher ratio with
regard to clkout could sample at a lower frequency. Data rate of 20 MByte/s
in the 1:3 case should be substainable on a fast PC. Data rate of 30 MByte/s
in the 1:2 is ambigious especially without the availability of deeper
buffers.
Setting the sampling ratio of CLKOUT to sampling frequency would require
some signaling. Perhaps a synchronous fifo write cycle to some
programmable divider could set the ratio.
But all this needs substantial external logic, making the approach less
attractive.
Bye
--
Uwe Bonnes bon@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
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