libftdi Archives

Subject: Driving open collector in mpsse mode & i2c woes

From: "Matt" <lists@xxxxxxxxxxxxxxx>
To: libftdi@xxxxxxxxxxxxxxxxxxxxxxx
Date: Tue, 10 Jan 2012 10:52:26 -0000
Hi all,

Does anybody know how to make an FTDI device (excluding the FT232 because
it has an MPSSE command) drive open collector (or open drain) when
configured in MPSSE mode? When running in MPSSE mode and implementing I2C,
my FT4232 device drives high and low which is unnecessary and may also
cause hw problems on other devices. I can't find anything that indicates
this is possible but ironically, FTDI app note 113 states that I2C relies
upon open collector outputs.

Also, when the three-phase clock is enabled (app notes state that this
should be used for I2C) to make sure data is available on rising or
falling edges, I see bus contention when the I2C slave I've addressed
pulls SDA low to generate an ACK. I set SDA as an input in order to read
the (N)ACK from the slave but the FT4232 does not stop driving the SDA
line until half way through the clock cycle but the slave attempts to
drive it low on the falling clock edge which results in contention. The
result is that there is a 'step' in the SDA line which is around the
switching threshold. This could easily be interpreted by other slave
devices as a start condition and would interfere with their hw driven
state machines. If I disable the three-phase clock, I don't see the
contention (since the FTDI device stops driving SDA on the falling edge
and the slave can safely drive it low to generate the ACK).

Lastly, in MPSSE mode, AFAICT it is impossible to to support clock
stretching - a required feature for an i2c master. The MPSSE clocks data
out on a bit or byte basis and does not seem to be configured to test if
the clock is low prior to driving it.

As a result of these pretty major shortfalls of MPSSE mode I've resorted
to bit banging to implement the I2C master protocol. This is 100% reliable
and can support clock stretching (which I struggle to see how this could
be implemented with MPSSE mode), drives SCL and SDA correctly (ie drives
low to generate a logic 0 and tristates to generate a logic 1). From what
I've found, an MPSSE does not appear to be able to implement i2c at all.

All of the implementations I've seen out there (eg libmpsse) do not
implement I2C properly because they don't (can't?) drive open collector
and don't (can't) support clock stretching.

Any thoughts? Much appreciated.

Cheers,
--  Matt


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