Hi Rick,
Here’s my analysis (including interface FSMs and block diagrams)
https://www.ovro.caltech.edu/~dwh/correlator/pdf/ftdi.pdf
https://www.ovro.caltech.edu/~dwh/correlator/pdf/ftdi_spi.pdf
The FT2232H can easily burst at 60MB/s. The doc has SignalTap II traces demonstrating it.
I wrote the original code in VHDL for Altera devices (using their counter primitives and so on). Since you’re targeting Lattice devices it might be easier to
code it from scratch (the FSMs can be re-coded from the ASM charts in the document – I create those before writing VHDL or SystemVerilog code).
If I needed this interface now, I’d code it in SystemVerilog and replace the Avalon-ST interface with the AXI4-Stream interface (which is literally identical,
but does not use the start-of-packet flag).
If you want the VHDL code, just ask … and I’ll try to be more organized and put it on github
J
Cheers,
Dave
Hi libftdi developers,
I'm working on a 200Mb/s ring network built out of lattice FPGA chips using oversampled clock and data recovery.
I'd like to communicate with the master node using an FTDI 2232H synchronous FIFO. Basically, I'd like to burst command packets into the master node (a sequence of bytes), and then check for and
receive any reply bytes as available. The peak throughput of the network is 100mb/s, but I'd be happy to do 1/4 of that.
I found a promising open source verilog for the FPGA side:
https://github.com/6thimage/FT245_interface
Is there a known working example code for reading/writing from a synchronous USB2.0 chip? The example in the source code is read only with (as near as I can tell) issues on writing. I'd like the
speed of synchronous, but I'd be willing to start with asynch if that works too.
kind regards,
--
Rick Walker
libftdi - see http://www.intra2net.com/en/developer/libftdi for details.
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