libftdi Archives

Subject: Clock Signal issues

From: "Chaves, Kevin" <kevin.chaves@xxxxxxxxxxxxxxxx>
To: "libftdi@xxxxxxxxxxxxxxxxxxxxxxx" <libftdi@xxxxxxxxxxxxxxxxxxxxxxx>
Date: Wed, 10 Jul 2013 13:27:10 -0400
 Hi,
 
 So I've been working with an FT2232H chip for about a week now, and libftdi=
  for 2 days. We had an issue with the libMPSSE_spi with linux so I decided =
 to switch to libftdi. I grabbed some source code for using the chip in spi =
 master mode.
 
 We have two really small issues and I'm wondering if there is a way to conf=
 igure the library to clean up.=20
 
 1. Clock signal=20
 I think I'm screwed with this one, since its a clock divisor. We need 8Mhz =
 but it seems to jump between 7.5 and 10, going from 7000000 and 8000000 as =
 inputs. I'm guessing I might be able to get it closer but hitting 8 might n=
 ot be possible.
 
 2. Small pauses in the clock..
 Each byte written there is a small pause before the next burst of 8, its ve=
 ry very small but we aren't sure why this is happening. The libMPSSE didn't=
  do this but it also didn't work beyond 50khz... so maybe it wasn't as noti=
 ceable there.
 
 3. Large pause before read
 I think i know why this is happening and there isn't much I can do about it=
 . There is a long pause between writing the command and reading the data. T=
 his likely is because the library I'm using is calling write then read, so =
 its probably more likely having to do with the cpu cycle and driver stack t=
 han it is the chip. But I could be wrong. Our spi device expects to shoot t=
 he data back out immediately.=20
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