John Oyler wrote:
>> If both ADBUS3 and 4 are low, it's as if I selected ADBUS3. I've
>> had some decent luck moving data both in and out for that (NSS_CONFIG,
>> the radio's config registers, a few read-onlys).
>>
>> I've yet to have any luck with reading from NSS_DATA (the radio's
>> fifo where it stores incoming packets, or where you write to to
>> send out packets). But I think this gives a clearer picture.
>>
>> http://imgur.com/6rsEb.jpg (My apologies for the image quality... I have
a crappy camera phone.)
>>
>> As you can see, ADBUS4 goes low, the clock starts wiggling...
>> MOSI and MISO are both low. ADBUS3/CS is high... so my chip selects are
where I want them to be.
The image quality is ok for now. I don't know how to interpret ADBUS7, so I
hope that doesn't matter. Once you get MOSI or MISO to toggle, though, I
may need a zoomed in shot.
>> Now, it could *possibly* be that there's no data to read... but
>> on the serial port version of this radio, I'm seeing a packet
>> coming in about every second here in the office. And since I
>> keep trying to read one byte at a time, for as long as several
>> minutes, I should get *something*. All zeros, the whole way.
Which commands (particularly the 0x80 commands) are you sending to get this
display? It would be nice to have the list of I/O bytes that go with the
screenshot.
>> Another possibility is that the radio's not in receive mode, but
>> this seems even less likely than that there are no packets in the fifo.
Is there a register you can read that states how many bytes are in the FIFO,
or at least whether or not it's empty?
>> The other thing is, in the data sheet it says "To read bytes from the
FIFO the
>> timing diagram below should be carefully followed by the uC." So, maybe
I'm not
>> doing it as perfect as I should be, my code is still rather sloppy.
They probably mean exactly what I was saying about +ve/-ve edges and that
sort of thing, and, because there are no transitions on MOSI/MISO, that
isn't causing the current problem you showed. Minimum times may also
matter, but are not shown on that diagram. Are you sure that your FTDI SPI
clock speed is low enough that the radio chip can keep up (i.e., is your
divisor high enough)?
>> To look at their diagram, the clock starts up no more than 1 cycle after
ADBUS4
>> goes low. But on the scope, I'm seeing at least 3 or 4 cycles worth. Is
that the
>> problem?
It usually isn't a problem with most chips. It shouldn't be counting when
the SCK channel isn't doing anything. I don't know if it's a problem with
this chip.
>> And how do I tell this dumb thing to toggle high again more quickly?
I don't see it toggling high again at all. Is that off the right hand side
of the screen? Even on the zoomed-out part at the top, which is admittedly
difficult to read, it doesn't seem to be going back high. And if you have a
question like that, I'd need to see exactly when the bytes are being sent
from the computer to the 2232, etc. You should certainly try to send the
bit-bang/MPSSE command to raise the line in the same buffer where you tell
it to do the SPI stuff.
Michael
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