>>>>> "Gerd" == Gerd v Egidy <gerd.von.egidy@xxxxxxxxxxxxx> writes:
Gerd> Hi Uwe,
>> Appended smal patch adds the bitmode (0x40) fot synchronous fifo mode
>> of the FT2232h
Gerd> Thanks for the patch.
Gerd> Is that the new 60 MHz mode introduced with the new H chips? Those
Gerd> many different modes of the H chips sometimes confuse me...
Yes, that the fast mode.
Gerd> Just read the datasheet of the FT2232H again and stumbled at this:
Gerd> Note that Asynchronous FIFO mode must be selected on both channels
Gerd> before selecting the Synchronous FIFO mode in software.
Gerd> (last sentence of chapter 4.4, page 25).
Gerd> So there seems to be needed more that just one call to
Gerd> ftdi_set_bitmode(). Since you seem to be experimenting with this
Gerd> mode - do you happen to have a short code snipped available which
Gerd> we could drop into the examples-dir?
Both channels need to be set to 245 FIFO mode in the EEPROM. Channel B
should be unused. Then setting Channel A to BITMODE_SYNCFF is enough to see
the 60 MHz CLKOUT on ACBUS5. This 60 MHz clock is
an indication that the chip is in synchronous FIFO mode, as described in
AN130. In fact, my test code is an modification of another example, and I
will upload hopefully soon after cleanup. I have already seen the 60 MHz
clock with the testcode on my demoboard.
Hopefully I will also have some speed measurements also, but the FPGA codes
still needs to be finished. Synchronisation between the FT2232 and the FPGA
is some problem and I will try following approch:
- if the 60 MHz fail, always reset the TX fifo in the fpga and only start
again when the clock reappears
- if the PC doesn't receive for some time, force TX Fifo reset be leaving
synchronous fifo mode and reenter synchronous mode. This should detect e.g.
FPGA reconfiguration
and resync both sides
Bye
--
Uwe Bonnes bon@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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