clk/2 -> 2
From /2, 0.125 steps may be taken.
The fractional part has frac_code encoding
+
+ value[13:0] of value is the divisor
+ index[9] mean 12 MHz Base(120 MHz/10) rate versus 3 MHz (48 MHz/16) else
+
+ H Type have all features above with
+ {index[8],value[15:14]} is the encoded subdivisor
+
+ FT232R, FT2232 and FT232BM have no option for 12 MHz and with
+ {index[0],value[15:14]} is the encoded subdivisor
+
+ AM Type chips have only four fractional subdivisors at value[15:14]
+ for subdivisors 0, 0.5, 0.25, 0.125
*/
static int ftdi_to_clkbits(int baudrate, unsigned int clk, int clk_div, unsigned long *encoded_divisor)
{
const calc_result *res = &baudrate.second;
- unsigned short divisor = calc_value & 0x3ff;
- unsigned short fractional_bits = (calc_index & 0x100) ? 4 : (calc_value >> 12);
- unsigned short clock = (calc_index & 0x100) ? 120 : 48;
-
+ unsigned short divisor = calc_value & 0x3fff;
+ unsigned short fractional_bits = (calc_value >> 14);
+ unsigned short clock = (calc_index & 0x200) ? 120 : 48;
+
+ switch (ftdi->type)
+ {
+ case TYPE_232H:
+ case TYPE_2232H:
+ case TYPE_4232H:
+ fractional_bits |= (calc_index & 0x100) ? 4 : 0;
+ break;
+ case TYPE_R:
+ case TYPE_2232C:
+ case TYPE_BM:
+ fractional_bits |= (calc_index & 0x001) ? 4 : 0;
+ break;
+ default:;
+ }
// Aid debugging since this test is a generic function
BOOST_CHECK_MESSAGE(res->actual_baudrate == calc_baudrate && res->divisor == divisor && res->fractional_bits == fractional_bits
&& res->clock == clock,